1. Field of the Invention
The present invention relates to a method for fabricating a transistor, and more particularly, to a method for fabricating a transistor having an elevated source/drain construction.
2. Discussion of the Related Art
A conventional elevated source/drain transistor is shown in FIGS. 1A through 1D.
Referring to FIG. 1A, a conventional elevated source/drain transistor includes a gate insulation film 12 formed on a silicon substrate 10. A poly-silicon film 14 is deposited on the gate insulation film 12. The poly-silicon film 14 is etched so as to expose a predetermined portion of the gate insulation film 12. Thus, a poly-silicon gate 14' is formed, as shown on FIG. 1B. An oxide film (first insulation film 16) is deposited on the gate insulation film 12 and the gate 14' through a chemical vapor deposition method.
Thereafter, as shown in FIG. 1C, a first insulation side wall spacer 16' is formed at a side surface of the poly-silicon gate 14' by etching-back the first insulation film 16 without using a mask. A predetermined portion of the surface of the silicon substrate 10 is exposed by etching a corresponding portion of the gate insulation film using the first insulation side wall spacer 16' as a mask.
Next, as shown in FIG. 1D, an epitaxial layer is selectively deposited on the surface of the exposed silicon substrate 10, and a source/drain 18 is formed by ion-implanting n.sup.+ or p.sup.+ impurity into the deposited epitaxial layer.
However, the transistor fabricated in the above-explained method has a disadvantage in that a short channel effect may occur due a pattern size reduction as the integration scale of the semiconductor device becomes larger.